FET biasing

Unlike BJTs, thermal runaway does not occur with FETs, as already discussed in our blog. However, the wide differences in maximum and minimum transfer characteristics make I_D levels unpredictable with simple fixed-gate bias voltage. To obtain reasonable limits on quiescent drain currents I_D and drain-source voltage V_DS, source resistor and potential divider bias techniques must be used. With few exceptions, MOSFET bias circuits are similar to those used for JFETs. Various FET biasing circuits are discussed below:

Fixed Bias.

Fixed bias-FET

DC bias of a FET device needs setting of gate-source voltage V_GS to give desired drain current I_D . For a JFET drain current is limited by the saturation current I_DS. Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.

Fixed dc bias is obtained using a battery V_QG. This battery ensures that the gate is always negative with respect to source and no current flows through resistor R_G and gate terminal that is I_G =0. The battery provides a voltage V_GS to bias the N-channel JFET, but no resulting current is drawn from the battery V_GG. Resistor R_G is included to allow any ac signal applied through capacitor C to develop across R_G. While any ac signal will develop across R_G, the dc voltage drop across R_G is equal to I_G R_G i.e. 0 volt.

The gate-source voltage V_GS is then

V_GS = - v_G – v_s = – v_GG – 0 = – V_GG

The drain -source current I_D is then fixed by the gate-source voltage as determined by equation.

This current then causes a voltage drop across the drain resistor R_D and is given as V_RD = I_D R_{D and output voltage, Vout = VDD – ID RD}

Self-Bias.

FET-Self Bias circuit

This is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in figure.

Since no gate current flows through the reverse-biased gate-source, the gate current I_G = 0 and, therefore,v_G = i_G R_G = 0

With a drain current I_D the voltage at the S is
V_s= I_D R_s

The gate-source voltage is then

V_Gs = V_G - V_s = 0 – I_D R_s = – I_D R_s

So voltage drop across resistance R_s provides the biasing voltage V_Gg and no external source is required for biasing and this is the reason that it is called self-biasing.

The operating point (that is zero signal I_D and V_DS) can easily be determined from equation and equation given below :

V_{DS =} V_DD – I_D (R_{D +} R_S)

Thus dc conditions of JFET amplifier are fully specified. Self biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like transconductance. Let the given JFET be replaced by another JFET having the double conductance then drain current will also try to be double but since any increase in voltage drop across R_s, therefore, gate-source voltage, V_GSbecomes more negative and thus increase in drain current is reduced.

Potential-Divider Biasing.

fet-potential-divider-biasing

A slightly modified form of dc bias is provided by the circuit shown in figure. The resistors R_Gl and R_G2 form a potential divider across drain supply V_DD. The voltage V₂ across R_G2 provides the necessary bias. The additional gate resistor R_Gl from gate to supply voltage facilitates in larger adjustment of the dc bias point and permits use of larger valued R_S.

The gate is reverse biased so that I_G = 0 and gate voltage

V_G =V₂ = (V_DD/R _{G1 +} R _G2 ) *R_G2

And

V_GS = v_G – v_s = V_G - I_D R_s

_{The circuit is so designed that ID Rs is greater than VG so that VGS is negative. This provides correct bias voltage.}

The operating point can be determined as

I_D = (V₂ – V_GS)/ R_S

And

V_DS = V_DD – I_D (R_D + R_S)